In a conventional semiconductor device manufacturing process, a plasma etching process is performed by using, e.g., a photoresist or the like as a mask, to thereby form an etching target film such as a silicon oxide film or the like in a desired pattern. As for the plasma etching apparatus, there is known, e.g., a capacitively coupled plasma etching apparatus for generating a plasma by applying a RF (radio frequency) power between a lower electrode also serving as a mounting table for mounting thereon a substrate such as a semiconductor wafer and an upper electrode disposed to face the lower electrode.
In such plasma etching for forming a hole in an insulating film such as a silicon oxide film, a silicon nitride film or the like, a film thickness of a mask tends to be decreased while the depth of the hole is increased, so that it is difficult to obtain a vertical hole shape.
Thus, various developments are being made in order to obtain desired opening characteristics and selectivity in the plasma etching process. For example, there is proposed a technique for obtaining desired opening characteristics and selectivity by applying a DC voltage to the upper electrode in the capacitively coupled plasma etching apparatus (see, e.g., Patent Document 1).    Patent Document 1: Japanese Patent Application Publication No. 2008-21791
As described above, it is required to develop a technique capable of performing etching for forming a hole having a large depth in a desired shape in the plasma etching process.